Research Staff Member of the IBM Research Divisio in T. J. Watson Research Center
In this seminar, we present a 10nm CMOS platform technology for low power and high perfor-mance applications with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrates. A 0.053um2 SRAM bit-cell is reported with a corresponding Static Noise Margin (SNM) of 140mV at 0.75V. Intensive multi-patterning technology and various self-aligned processes have been developed with 193i lithography to overcome optical patterning limits. Multi-workfunction (MWF) gate stack has been enabled to pro-vide Vt tunability without the variability degradation induced by Random Dopant Fluctuation (RDF) from channel dopants.
Dr. Guo received his B.S. degree in Microelectronics in Peking University in 2002, and Ph.D. degree in Electrical Engi-neering from Yale University in 2007. In 2007, he joined the IBM Research Division in T. J. Watson Research Center as Re-search Staff Member.
Dr. Guo spent first few years in IBM focusing on Gate-First High-K/Metal Gate R&D, qualified High-K/Metal Gate Technology for IBM Alliance's 32nm/28nm CMOS Technologies. From 2010 to 2013, Dr. Guo took team lead roles in 22nm and 10nm CMOS Device Design. His research and development focused on exploring new material and structure options for competitive CMOS technologies. In 2013, Dr. Guo become the manager of Advanced CMOS Device Research Group. This group is focusing on leading edge technology definition, device design, and device integration, including 10nm node, 7nm node and beyond.
Dr. Guo was the recipient of 2013 IBM Corporate Award for his work in Fundamental Research in High-K/Metal Gate Technology, and 2012 IBM Research Division Team Excellence and Eminence Award for his work in 22nm Gate First Project. Dr. Guo has authored and co-authored over 30 technical jour-nal papers and conference publications. He has 116 patents issued or filed.