2018年11月7日上午，美国普渡大学电气与计算机工程学院叶培德教授应邀访问微纳电子学研究院，在微纳电子大厦103报告厅做了题为 “Steep-Slope Hysteresis-Free Negative-Capacitance 2D Transistors”的学术报告。
Steep-Slope Hysteresis-Free Negative-Capacitance 2D Transistors
The so-called Boltzmann Tyranny defines the fundamental thermionic limit of the subthreshold slope (SS) of a metal-oxide-semiconductor field-effect transistor (MOSFET) at 60 mV/dec at room temperature and, therefore, precludes the lowering of the supply voltage and the overall power consumption . Adding a ferroelectric negative capacitor to the gate stack of a MOSFET may offer a promising solution to bypassing this fundamental barrier . Meanwhile, two-dimensional (2D) semiconductors, such as atomically thin transition metal dichalcogenides (TMDs) due to their low dielectric constant, and ease of integration in a junctionless transistor topology, offer enhanced electrostatic control of the channel. Here, we combine these two advantages and demonstrate for the first time a molybdenum disulfide (MoS2) 2D steep slope transistor with a ferroelectric hafnium zirconium oxide layer (HZO) in the gate dielectric stack . This device exhibits excellent performance in both on- and off-states, with maximum drain current of 510 μA/μm, sub-thermionic subthreshold slope and is essentially hysteresis-free. Negative differential resistance (NDR) was observed at room temperature in the MoS2 negative capacitance field-effect-transistors (NC-FETs) as the result of negative capacitance due to the negative drain-induced-barrier-lowering (DIBL). High on-current induced self-heating effect was also observed and studied. We will also discuss the effect of internal metal gate [4,5], p-type 2D transistors , and ferroelectric switch speed issues  in this talk. The work is in close collaborations with Mengwei Si, Wonil Chung, Chun-Jung Su, Chunsheng Jiang, Hong Zhou, Kerry D. Maize, Ali Shakouri, Muhammad A. Alam.