师资力量

马宇飞

职称:研究员

研究所:微纳电子学研究院、人工智能研究院

研究领域:集成电路设计、FPGA硬件加速、人工智能芯片架构

电子邮件:yufei.ma@pku.edu.cn

 

 

教育/科研经历

2011年于南京航空航天大学本科毕业,2013年获美国宾夕法尼亚大学硕士学位,2018年获美国亚利桑那州立大学电子工程博士学位,2018年在美国飞步科技有限公司担任高级工程师,2019年在南京大学电子科学与工程学院担任副研究员。

2020年加入北京大学微纳电子学系和人工智能研究院,担任研究员、博士生导师。

研究简介

在计算机硬件、超大规模数字集成电路设计和相应算法同步优化等领域进行了长期而深入的研究,特别是深度学习算法的高效硬件部署和加速方面。相关成果发表在IEEE TCAD、TVLSI、JETCAS等集成电路设计和自动化领域的一流学术期刊,以及IEEE/ACM ICCAD、ACM/SIGDA FPGA、IEEE ISCAS等本行业旗舰会议。学术成果获得国际同行肯定,目前SCI他引量150多次,谷歌学术引用量800多次。担任IEEE TVLSI、IEEE TC、IEEE TCAS-I/II、DAC等诸多高水平期刊和会议的审稿专家。

本课题组长期招收1)集成电路芯片设计、2)FPGA系统开发、3)深度学习算法优化等方向的博士后、博士/硕士研究生、本科生;欢迎感兴趣的同学将简历等资料发邮箱yufei.ma@pku.edu.cn

代表性论文

  • Y. Ma, Y. Cao, S. Vrudhula, and J. Seo, “Performance Modeling for CNN Inference Accelerators on FPGA,” In IEEE Trans. on Computer-Aided Design (CAD) of Integrated Circuits and Systems, 2020.
  • Y. Ma, Y. Cao, S. Vrudhula, and J. Seo, “Automatic Compilation of Diverse CNNs onto High-Performance FPGA Accelerators,” In IEEE Trans. on Computer-Aided Design (CAD) of Integrated Circuits and Systems, 2019.
  • Y. Ma, Y. Cao, S. Vrudhula, and J. Seo, “Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA,” In IEEE Trans. on Very Large Scale Integration (VLSI) Systems, 2018.
  • Y. Ma, N. Suda, Y. Cao, S. Vrudhula, and J. Seo, “ALAMO: FPGA Acceleration of Deep Learning Algorithms with a Modularized RTL Compiler,” In Integration, VLSI Journal, 2017.
  • Y. Ma, T. Zheng, Y. Cao, S. Vrudhula, and J. Seo, "Algorithm-Hardware Co-Design of Single Shot Detector for Fast Object Detection on FPGAs,” In IEEE/ACM Int. Conf. on Computer-Aided Design (ICCAD), 2018.
  • Y. Ma, Y. Cao, S. Vrudhula, and J. Seo, “An Automatic RTL Compiler for High-Throughput FPGA Implementation of Diverse Deep Convolutional Neural Networks,” In Int. Conf. Field-Programmable Logic and Applications (FPL), 2017.
  • Y. Ma, M. Kim, Y. Cao, S. Vrudhula, and J. Seo, “End-to-End Scalable FPGA Accelerator for Deep Residual Networks,” In IEEE Int. Symp. on Circuits and Systems (ISCAS), 2017.
  • Y. Ma, Y. Cao, S. Vrudhula, and J. Seo, “Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks,” In ACM/SIGDA Int. Symp. on Field-Programmable Gate Arrays (FPGA), 2017.
  • Y. Ma, N. Suda, Y. Cao, J. Seo, and S. Vrudhula, “Scalable and modularized RTL compilation of Convolutional Neural Networks onto FPGA,” In Int. Conf. Field-Programmable Logic and Applications (FPL), 2016.